1. Field of the Invention
This invention relates to a clamping circuit and more particularly a clamping circuit for use with integrated circuits.
2. Description of the Prior Art
In the past, numerous circuit techniques have been employed for clamping purposes. A fundamental technique is to clamp a circuit node to a desired clamping voltage by means of a single diode. However, when the diode is driven to a lower impedance or higher conductive state, the forward voltage drop of the diode introduces a error signal and thus the circuit node never can be ideally clamped to ground potential.
An improvement to the diode clamp is a "current-mirror" clamping circuit. The emitter terminal of the transistor is coupled to the clamping node and its base terminal is connected to the anode terminal of a matching semiconductor diode. The cathode terminal of the diode is then connected to the desired clamping voltage, such as, ground potential. Assuming the clamping transistor possesses an extremely high beta, i.e., base current is negligable, essentially equal amounts of current will flow through the transistor and the semiconductor diode when the clamping node is being driven into its low impedance state. In an integrated circuit implementation the impedance characteristic of the base-to-emitter junction of the clamping transistor is identical to the diode drop impedance characteristic and thus the emitter terminal of the clamping transistor is maintained at ground potential as the voltage loop equation beginning at the cathode of the diode and down through the base emitter junction of the clamping transistor results in the emitter terminal being maintained at the same potential as the cathode terminal of the diode, or ground potential in the present example.
Notwithstanding, it can be seen for certain circuit applications the conventional "current-mirror" clamping circuit suffers from inherent drawbacks. For example, with an NPN clamping transistor a large negative noise spike at its emitter terminal causes substantially increased current flow through the clamping transistor without a concomitant increase of current flow through the diode. As a result, there is a more negative voltage drop across the base-to-emitter junction of the transistor than the voltage drop across the diode. Accordingly, the circuit node which is being clamped is capable of swinging below ground potential. With the current flow through the clamping transistor 10 and 100 times greater than the current flow through the diode, the emitter terminal is capable of being driven to -60 and -120 millivolts, respectively. For many circuit applications these negative excursions are not tolerable. In an integrated circuit environment, as illustrated in FIG. 1, one common integrated circuit implementation employs a starting P-type substrate 10 and an overlying N epitaxial layer 12 for both NPN and PNP transistors. A PNP transistor 14 is formed by diffusing a P-type region 16 into the N epitaxial layer 12. Similarly, the integrated circuit also contains NPN transistors schematically designated at 18 located in a P+ isolation region 20 and is formed by first diffusing a P base region 22 into the N epitaxial layer 12 in order to form a PN base collector junction. An N type region 24 is then diffused into the P region 22 in order to form the emitter of the NPN transistor 18.
In this integrated circuit environment it can be seen that if the base collector junction of PNP transistor 14 is forward biased, for example, by a large negative noise spike, carriers are injected into the P substrate at the PN junction depicted at 26. This effectively forms a lateral parasitic NPN transistor constituted by the N base region of transistor 14, the P substrate region, and the N collector region of transistor 18, as schematically depicted by solid line 28. Thus, with a large negative signal applied to PNP transistor 14 a sneak path is created to another NPN transistor located on the integrated circuit substrate. This sneak path is capable of erroneously triggering other semiconductor devices located on the circuit.